`timescale 1ns / 1ps

module fishnet_pe192
#(
    parameter N_IN      = 4,
    parameter N_OT      = 1,
    parameter BIT_IM    = 8,
    parameter BIT_CV    = 16
)
(
    input   clk,
    input   rst_n,
    
    input   i_vld,
    output  i_rdy,
    input   [N_IN*BIT_IM-1 : 0]      i_data,
    
    output  o_vld,
    input   o_rdy,
    output  [N_OT*BIT_CV-1 : 0]      o_data
);

localparam ROW_0 = 360;
localparam ROW_1 = 160;
localparam ROW_2 = ROW_1 / 2;
localparam ROW_3 = ROW_2 / 2;
localparam ROW_4 = ROW_3 / 2;

localparam COL_0 = 640;
localparam COL_1 = 320;
localparam COL_2 = COL_1 / 2;
localparam COL_3 = COL_2 / 2;
localparam COL_4 = COL_3 / 2;

localparam NCH_0 = 3;
localparam NCH_1 = 48;
localparam NCH_2 = 96;
localparam NCH_3 = 192;
localparam NCH_4 = 384;
localparam NCH_5 = 512;
localparam NCH_6 = 4 * NCH_3 + NCH_5;   // 1280
localparam NCH_7 = 96;
localparam NCH_8 = 10;

localparam NIO_0 = 1;
localparam NIO_1 = 4;
localparam NIO_2 = 2;
localparam NIO_3 = 1;
localparam NIO_4 = 1;
localparam NIO_5 = 2;
localparam NIO_6 = 1;
localparam NIO_7 = 1;

localparam BP_CH = 4 * NCH_3;
localparam BP_IO = NIO_5;

wire rst;
assign rst = ~rst_n;

wire l0_rdy;
wire l0_vld;
wire [N_IN * BIT_IM - 1 : 0] l0_data;

assign i_rdy = l0_rdy;
assign l0_vld = i_vld;
assign l0_data = i_data;

wire r0_rdy;
wire r0_vld;
wire [NIO_0 * BIT_IM - 1 : 0] r0_data;

reduce2 #(
    .N      ( N_IN / NIO_0   ),
    .WIDTH  ( NIO_0 * BIT_IM )
)
inst_reduce (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( l0_rdy   ),
    .i_vld                   ( l0_vld   ),
    .i_data                  ( l0_data  ),

    .o_rdy                   ( r0_rdy   ),
    .o_vld                   ( r0_vld   ),
    .o_data                  ( r0_data  )
);

wire l1_rdy;
wire l1_vld;
wire [NIO_1 * BIT_IM - 1 : 0] l1_data;

dwpw_layer #(
    .N_IN          ( NIO_0          ),
    .N_OT          ( NIO_1         ),
    .N_ICH         ( NCH_0         ),
    .N_OCH         ( NCH_1         ),
    .BIT_IM        ( 8             ),
    .BIT_WT        ( 5             ),
    .BIT_CV        ( 16            ),
    .BIT_NB        ( 16            ),
    .BIT_NM        ( 16            ),
    .ROW           ( ROW_1         ),
    .COL           ( COL_1         ),
    .DW_INW        ( 3             ),
    .DW_ACT        ( 1             ),
    .DW_PAD        ( 128           ),
    .DWCV_PE       ( "DSP"         ),
    .DWET_FILE     ( "L0_DW.mem"   ),
    .DWET_TYPE     ( "distributed" ),
    .DWET_LATENCY  ( 1             ),
    .DBUF_TYPE     ( "block"       ),
    .DBUF_LATENCY  ( 2             ),
    .DNORM_PE      ( "DSP"         ),
    .DNORM_FILE    ( "L0_BM.mem"   ),
    .DNORM_TYPE    ( "distributed" ),
    .DNORM_LATENCY ( 1             ),
    .PW_INH        ( 1             ),
    .PW_INW        ( 3             ),
    .PW_OUT        ( 4             ),
    .PW_ACT        ( 4             ),
    .PWCV_PE       ( "DSP"         ),
    .PWET_FILE     ( "L1_PW.mem"   ),
    .PWET_TYPE     ( "distributed" ),
    .PWET_LATENCY  ( 1             ),
    .PBUF_TYPE     ( "register"    ),
    .PBUF_LATENCY  ( 1             ),
    .PNORM_PE      ( "DSP"         ),
    .PNORM_FILE    ( "L1_BM.mem"   ),
    .PNORM_TYPE    ( "distributed" ),
    .PNORM_LATENCY ( 1             ),
    .PFIFO_TYPE    ( "none"        ),
    .PFIFO_LATENCY ( 0             )
) inst_dwpw_1 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( r0_rdy   ),
    .i_vld                   ( r0_vld   ),
    .i_data                  ( r0_data  ),

    .o_rdy                   ( l1_rdy   ),
    .o_vld                   ( l1_vld   ),
    .o_data                  ( l1_data  )
);

wire p1_rdy;
wire p1_vld;
wire [NIO_1 * BIT_IM - 1 : 0] p1_data;

maxpool_layer #(
    .N_IO  ( NIO_1    ),
    .N_CH  ( NCH_1    ),
    .N_COL ( COL_1    ),
    .BIT   ( BIT_IM   )
) inst_pool_1 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( l1_rdy   ),
    .i_vld                   ( l1_vld   ),
    .i_data                  ( l1_data  ),

    .o_rdy                   ( p1_rdy   ),
    .o_vld                   ( p1_vld   ),
    .o_data                  ( p1_data  )
);

wire l2_rdy;
wire l2_vld;
wire [NIO_2 * BIT_IM - 1 : 0] l2_data;

dwpw_layer #(
    .N_IN          ( NIO_1         ),
    .N_OT          ( NIO_2         ),
    .N_ICH         ( NCH_1         ),
    .N_OCH         ( NCH_2         ),
    .BIT_IM        ( 8             ),
    .BIT_WT        ( 5             ),
    .BIT_CV        ( 16            ),
    .BIT_NB        ( 16            ),
    .BIT_NM        ( 16            ),
    .ROW           ( ROW_2         ),
    .COL           ( COL_2         ),
    .DW_INW        ( 8             ),
    .DW_ACT        ( 1             ),
    .DW_PAD        ( 0             ),
    .DWCV_PE       ( "DSP"         ),
    .DWET_FILE     ( "L2_DW.mem"   ),
    .DWET_TYPE     ( "distributed" ),
    .DWET_LATENCY  ( 1             ),
    .DBUF_TYPE     ( "block"       ),
    .DBUF_LATENCY  ( 2             ),
    .DNORM_PE      ( "DSP"         ),
    .DNORM_FILE    ( "L2_BM.mem"   ),
    .DNORM_TYPE    ( "distributed" ),
    .DNORM_LATENCY ( 1             ),
    .PW_INH        ( 4             ),
    .PW_INW        ( 3             ),
    .PW_OUT        ( 6             ),
    .PW_ACT        ( 2             ),
    .PWCV_PE       ( "DSP"         ),
    .PWET_FILE     ( "L3_PW.mem"   ),
    .PWET_TYPE     ( "block"       ),
    .PWET_LATENCY  ( 2             ),
    .PBUF_TYPE     ( "distributed" ),
    .PBUF_LATENCY  ( 1             ),
    .PNORM_PE      ( "DSP"         ),
    .PNORM_FILE    ( "L3_BM.mem"   ),
    .PNORM_TYPE    ( "distributed" ),
    .PNORM_LATENCY ( 1             ),
    .PFIFO_TYPE    ( "block"       ),
    .PFIFO_LATENCY ( 2             )
) inst_dwpw_2 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( p1_rdy   ),
    .i_vld                   ( p1_vld   ),
    .i_data                  ( p1_data  ),

    .o_rdy                   ( l2_rdy   ),
    .o_vld                   ( l2_vld   ),
    .o_data                  ( l2_data  )
);

wire p2_rdy;
wire p2_vld;
wire [NIO_2 * BIT_IM - 1 : 0] p2_data;

maxpool_layer #(
    .N_IO  ( NIO_2    ),
    .N_CH  ( NCH_2    ),
    .N_COL ( COL_2    ),
    .BIT   ( BIT_IM   )
) inst_pool_2 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( l2_rdy   ),
    .i_vld                   ( l2_vld   ),
    .i_data                  ( l2_data  ),

    .o_rdy                   ( p2_rdy   ),
    .o_vld                   ( p2_vld   ),
    .o_data                  ( p2_data  )
);

wire l3_rdy;
wire l3_vld;
wire [NIO_3 * BIT_IM - 1 : 0] l3_data;

dwpw_layer #(
    .N_IN          ( NIO_2         ),
    .N_OT          ( NIO_3         ),
    .N_ICH         ( NCH_2         ),
    .N_OCH         ( NCH_3         ),
    .BIT_IM        ( 8             ),
    .BIT_WT        ( 5             ),
    .BIT_CV        ( 16            ),
    .BIT_NB        ( 16            ),
    .BIT_NM        ( 16            ),
    .ROW           ( ROW_3         ),
    .COL           ( COL_3         ),
    .DW_INW        ( 4             ),
    .DW_ACT        ( 1             ),
    .DW_PAD        ( 0             ),
    .DWCV_PE       ( "DSP"         ),
    .DWET_FILE     ( "L4_DW.mem"   ),
    .DWET_TYPE     ( "block"       ),
    .DWET_LATENCY  ( 2             ),
    .DBUF_TYPE     ( "block"       ),
    .DBUF_LATENCY  ( 2             ),
    .DNORM_PE      ( "DSP"         ),
    .DNORM_FILE    ( "L4_BM.mem"   ),
    .DNORM_TYPE    ( "block"       ),
    .DNORM_LATENCY ( 2             ),
    .PW_INH        ( 4             ),
    .PW_INW        ( 3             ),
    .PW_OUT        ( 6             ),
    .PW_ACT        ( 1             ),
    .PWCV_PE       ( "DSP"         ),
    .PWET_FILE     ( "L5_PW.mem"   ),
    .PWET_TYPE     ( "block"       ),
    .PWET_LATENCY  ( 2             ),
    .PBUF_TYPE     ( "distributed" ),
    .PBUF_LATENCY  ( 1             ),
    .PNORM_PE      ( "DSP"         ),
    .PNORM_FILE    ( "L5_BM.mem"   ),
    .PNORM_TYPE    ( "block"       ),
    .PNORM_LATENCY ( 2             ),
    .PFIFO_TYPE    ( "block"       ),
    .PFIFO_LATENCY ( 2             )
) inst_dwpw_3 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( p2_rdy   ),
    .i_vld                   ( p2_vld   ),
    .i_data                  ( p2_data  ),

    .o_rdy                   ( l3_rdy   ),
    .o_vld                   ( l3_vld   ),
    .o_data                  ( l3_data  )
);

wire s3_vld, s3_rdy;
wire [NIO_3 * BIT_IM -1 : 0] s3_data;

hs_fifo2 #(
    .WIDTH  ( NIO_3 * BIT_IM    )
) inst_skid_3 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( l3_rdy   ),
    .i_vld                   ( l3_vld   ),
    .i_data                  ( l3_data  ),

    .o_rdy                   ( s3_rdy   ),
    .o_vld                   ( s3_vld   ),
    .o_data                  ( s3_data  )
);

wire a3_rdy;
wire a3_vld;
wire [NIO_3 * BIT_IM - 1 : 0] a3_data;
wire b3_rdy;
wire b3_vld;
wire [NIO_3 * BIT_IM - 1 : 0] b3_data;

stream_copy #(
    .BIT    ( BIT_IM ),
    .N_IO   ( NIO_3  )
) inst_copy (
    .clk        ( clk       ),
    .rst        ( rst       ),

    .i_rdy      ( s3_rdy    ),
    .i_vld      ( s3_vld    ),
    .i_data     ( s3_data   ),

    .o0_rdy     ( a3_rdy    ),
    .o0_vld     ( a3_vld    ),
    .o0_data    ( a3_data   ),

    .o1_rdy     ( b3_rdy    ),
    .o1_vld     ( b3_vld    ),
    .o1_data    ( b3_data   )
);

wire tx_rdy;
wire tx_vld;
wire [BP_IO * BIT_IM - 1 : 0] tx_data;

generate
if (BP_IO > NIO_3) begin
    expand #(
        .N     ( BP_IO / NIO_3  ),
        .WIDTH ( NIO_3 * BIT_IM )
    ) inst_expand_tx (
        .clk                     ( clk      ),
        .rst                     ( rst      ),

        .i_rdy                   ( b3_rdy   ),
        .i_vld                   ( b3_vld   ),
        .i_data                  ( b3_data  ),

        .o_rdy                   ( tx_rdy   ),
        .o_vld                   ( tx_vld   ),
        .o_data                  ( tx_data  )
    );
end
else begin
    assign b3_rdy = tx_rdy;
    assign tx_vld = b3_vld;
    assign tx_data = b3_data;
end
endgenerate

wire p3_rdy;
wire p3_vld;
wire [NIO_3 * BIT_IM - 1 : 0] p3_data;

maxpool_layer #(
    .N_IO  ( NIO_3    ),
    .N_CH  ( NCH_3    ),
    .N_COL ( COL_3    ),
    .BIT   ( BIT_IM   )
) inst_pool_3 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( a3_rdy   ),
    .i_vld                   ( a3_vld   ),
    .i_data                  ( a3_data  ),

    .o_rdy                   ( p3_rdy   ),
    .o_vld                   ( p3_vld   ),
    .o_data                  ( p3_data  )
);

wire l4_rdy;
wire l4_vld;
wire [NIO_4 * BIT_IM - 1 : 0] l4_data;

dwpw_layer #(
    .N_IN          ( NIO_3         ),
    .N_OT          ( NIO_4         ),
    .N_ICH         ( NCH_3         ),
    .N_OCH         ( NCH_4         ),
    .BIT_IM        ( 8             ),
    .BIT_WT        ( 5             ),
    .BIT_CV        ( 16            ),
    .BIT_NB        ( 16            ),
    .BIT_NM        ( 16            ),
    .ROW           ( ROW_4         ),
    .COL           ( COL_4         ),
    .DW_INW        ( 2             ),
    .DW_ACT        ( 1             ),
    .DW_PAD        ( 0             ),
    .DWCV_PE       ( "DSP"         ),
    .DWET_FILE     ( "L6_DW.mem"   ),
    .DWET_TYPE     ( "block"       ),
    .DWET_LATENCY  ( 2             ),
    .DBUF_TYPE     ( "block"       ),
    .DBUF_LATENCY  ( 2             ),
    .DNORM_PE      ( "DSP"         ),
    .DNORM_FILE    ( "L6_BM.mem"   ),
    .DNORM_TYPE    ( "block"       ),
    .DNORM_LATENCY ( 2             ),
    .PW_INH        ( 4             ),
    .PW_INW        ( 3             ),
    .PW_OUT        ( 6             ),
    .PW_ACT        ( 1             ),
    .PWCV_PE       ( "DSP"         ),
    .PWET_FILE     ( "L7_PW.mem"   ),
    .PWET_TYPE     ( "block"       ),
    .PWET_LATENCY  ( 2             ),
    .PBUF_TYPE     ( "block"       ),
    .PBUF_LATENCY  ( 2             ),
    .PNORM_PE      ( "DSP"         ),
    .PNORM_FILE    ( "L7_BM.mem"   ),
    .PNORM_TYPE    ( "block"       ),
    .PNORM_LATENCY ( 2             ),
    .PFIFO_TYPE    ( "block"       ),
    .PFIFO_LATENCY ( 2             )
) inst_dwpw_4 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( p3_rdy   ),
    .i_vld                   ( p3_vld   ),
    .i_data                  ( p3_data  ),

    .o_rdy                   ( l4_rdy   ),
    .o_vld                   ( l4_vld   ),
    .o_data                  ( l4_data  )
);

wire l5_rdy;
wire l5_vld;
wire [NIO_5 * BIT_IM - 1 : 0] l5_data;

dwpw_layer #(
    .N_IN          ( NIO_4         ),
    .N_OT          ( NIO_5         ),
    .N_ICH         ( NCH_4         ),
    .N_OCH         ( NCH_5         ),
    .BIT_IM        ( 8             ),
    .BIT_WT        ( 5             ),
    .BIT_CV        ( 16            ),
    .BIT_NB        ( 16            ),
    .BIT_NM        ( 16            ),
    .ROW           ( ROW_4         ),
    .COL           ( COL_4         ),
    .DW_INW        ( 4             ),
    .DW_ACT        ( 1             ),
    .DW_PAD        ( 0             ),
    .DWCV_PE       ( "DSP"         ),
    .DWET_FILE     ( "L8_DW.mem"   ),
    .DWET_TYPE     ( "block"       ),
    .DWET_LATENCY  ( 2             ),
    .DBUF_TYPE     ( "block"       ),
    .DBUF_LATENCY  ( 2             ),
    .DNORM_PE      ( "DSP"         ),
    .DNORM_FILE    ( "L8_BM.mem"   ),
    .DNORM_TYPE    ( "block"       ),
    .DNORM_LATENCY ( 2             ),
    .PW_INH        ( 4             ),
    .PW_INW        ( 6             ),
    .PW_OUT        ( 8             ),
    .PW_ACT        ( 1             ),
    .PWCV_PE       ( "DSP"         ),
    .PWET_FILE     ( "L9_PW.mem"   ),
    .PWET_TYPE     ( "block"       ),
    .PWET_LATENCY  ( 2             ),
    .PBUF_TYPE     ( "block"       ),
    .PBUF_LATENCY  ( 2             ),
    .PNORM_PE      ( "DSP"         ),
    .PNORM_FILE    ( "L9_BM.mem"   ),
    .PNORM_TYPE    ( "block"       ),
    .PNORM_LATENCY ( 2             ),
    .PFIFO_TYPE    ( "block"       ),
    .PFIFO_LATENCY ( 2             )
) inst_dwpw_5 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( l4_rdy   ),
    .i_vld                   ( l4_vld   ),
    .i_data                  ( l4_data  ),

    .o_rdy                   ( l5_rdy   ),
    .o_vld                   ( l5_vld   ),
    .o_data                  ( l5_data  )
);

wire f5_rdy;
wire f5_vld;
wire [NIO_5 * BIT_IM - 1 : 0] f5_data;

zq_fifo #(
    .WIDTH      ( NIO_5 * BIT_IM    ),
    .DEPTH      ( NCH_5 / NIO_5 * 2 ),
    .RAMTYPE    ( "block"           ),
    .RAMLATENCY ( 2                 )
)
inst_fifo_L5 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .in_rdy                  ( l5_rdy   ),
    .in_vld                  ( l5_vld   ),
    .din                     ( l5_data  ),

    .out_rdy                 ( f5_rdy   ),
    .out_vld                 ( f5_vld   ),
    .dout                    ( f5_data  )
);

wire rx_rdy;
wire rx_vld;
wire [BP_IO * BIT_IM - 1 : 0] rx_data;

bypass_unit #(
    .BIT         ( BIT_IM   ),
    .N_IO        ( BP_IO    ),
    .N_CH        ( BP_CH    ),
    .COL         ( COL_4    ),
    .RAM_TYPE    ( "block"  ),
    .RAM_LATENCY ( 3        )
) inst_bypass (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( tx_rdy   ),
    .i_vld                   ( tx_vld   ),
    .i_data                  ( tx_data  ),

    .o_rdy                   ( rx_rdy   ),
    .o_vld                   ( rx_vld   ),
    .o_data                  ( rx_data  )
);

wire cb_rdy;
wire cb_vld;
wire [NIO_5 * BIT_IM - 1 : 0] cb_data;

stream_combine #(
    .BIT   ( BIT_IM ),
    .N_IO  ( NIO_5  ),
    .N_CH0 ( BP_CH  ),
    .N_CH1 ( NCH_5  )
) inst_combine (
    .clk                     ( clk       ),
    .rst                     ( rst       ),

    .i0_rdy                  ( rx_rdy    ),
    .i0_vld                  ( rx_vld    ),
    .i0_data                 ( rx_data   ),

    .i1_rdy                  ( f5_rdy    ),
    .i1_vld                  ( f5_vld    ),
    .i1_data                 ( f5_data   ),

    .o_rdy                   ( cb_rdy    ),
    .o_vld                   ( cb_vld    ),
    .o_data                  ( cb_data   )
);

wire l6_rdy;
wire l6_vld;
wire [NIO_6 * BIT_IM - 1 : 0] l6_data;

dwpw_layer_l6_pe192 #(
    .N_IN          ( NIO_5         ),
    .N_OT          ( NIO_6         ),
    .N_ICH         ( NCH_6         ),
    .N_OCH         ( NCH_7         ),
    .BIT_IM        ( 8             ),
    .BIT_WT        ( 5             ),
    .BIT_CV        ( 16            ),
    .BIT_NB        ( 16            ),
    .BIT_NM        ( 16            ),
    .ROW           ( ROW_4         ),
    .COL           ( COL_4         ),
    .DW_INW        ( 16            ),
    .DW_ACT        ( 2             ),
    .DW_PAD        ( 0             ),
    .DWCV_PE       ( "DSP"         ),
    .DWET_FILE     ( "L10_DW.mem"  ),
    .DWET_TYPE     ( "block"       ),
    .DWET_LATENCY  ( 2             ),
    .DBUF_TYPE     ( "block"       ),
    .DBUF_LATENCY  ( 2             ),
    .DNORM_PE      ( "DSP"         ),
    .DNORM_FILE    ( "L10_BM.mem"  ),
    .DNORM_TYPE    ( "block"       ),
    .DNORM_LATENCY ( 2             ),
    .PW_INH        ( 4             ),
    .PW_INW        ( 5             ),
    .PW_OUT        ( 6             ),
    .PW_ACT        ( 1             ),
    .PWCV_PE       ( "DSP"         ),
    .PWET_FILE     ( "L11_PW.mem"  ),
    .PWET_TYPE     ( "block"       ),
    .PWET_LATENCY  ( 2             ),
    .PBUF_TYPE     ( "block"       ),
    .PBUF_LATENCY  ( 2             ),
    .PNORM_PE      ( "DSP"         ),
    .PNORM_FILE    ( "L11_BM.mem"  ),
    .PNORM_TYPE    ( "block"       ),
    .PNORM_LATENCY ( 2             ),
    .PFIFO_TYPE    ( "block"       ),
    .PFIFO_LATENCY ( 2             )
) inst_dwpw_6 (
    .clk                     ( clk      ),
    .rst                     ( rst      ),

    .i_rdy                   ( cb_rdy   ),
    .i_vld                   ( cb_vld   ),
    .i_data                  ( cb_data  ),

    .o_rdy                   ( l6_rdy   ),
    .o_vld                   ( l6_vld   ),
    .o_data                  ( l6_data  )
);

wire l7_rdy;
wire l7_vld;
wire [NIO_7 * BIT_CV - 1 : 0] l7_data;

pwc2 #(
    .N_INH       ( 1            ),
    .N_INW       ( 1            ),
    .N_OUT       ( 1            ),
    .N_ICH       ( NCH_7        ),
    .N_OCH       ( NCH_8        ),
    .BIT_I       ( 8            ),
    .BIT_W       ( 5            ),
    .BIT_O       ( 16           ),
    .PE_TYPE     ( "LUT"        ),
    .ROM_TYPE    ( "block"      ),
    .ROM_FILE    ( "L12_PW_old.mem" ),
    .ROM_LATENCY ( 2            ),
    .RAM_TYPE    ( "block"      ),
    .RAM_LATENCY ( 2            )
) inst_pwc2_L7
(
    .clk        ( clk       ),
    .rst        ( rst       ),

    .i_rdy      ( l6_rdy    ),
    .i_vld      ( l6_vld    ),
    .i_data     ( l6_data   ),

    .o_rdy      ( l7_rdy    ),
    .o_vld      ( l7_vld    ),
    .o_data     ( l7_data   )
);

assign l7_rdy = o_rdy;
assign o_vld = l7_vld;
assign o_data = l7_data;

endmodule
